1. Field of the Invention
The present invention relates to an information recording and reproducing apparatus, or in particular to a technique for improving the detection rate of a data synchronizing (hereinafter referred to as “sync”) signal by improving the performance of data discrimination of a data sync signal section.
2. Description of the Related Art
FIG. 27 shows an example of the recording format in a magnetic disk device. Data are recorded or reproduced in and from each sector of a recording medium constituting a unit storage area. Each sector includes a PLO (phase locked oscillator) sync area 76 for pull-in of a PLL (phase locked loop), a data sync signal 77 for producing a decode timing signal for a modulated code by detecting the start position of the data, a data section 78 for actually recording and reproducing the data, and a CRC (cyclic redundancy check) or an ECC (error correcting code) 79 for detecting or correcting errors. A gap 80 constituting a pattern for absorbing various delay time is arranged between the sectors.
It is well known that accurate detection of the data sync signal 77 is very important for decoding the following data section 78. Even in the case where the data decoded in the data section 78 has a very good error rate, a detection error (i.e. failure to detect at the right position or detection at a wrong position) of the data sync signal 77 which is normally about several bytes will lead to the failure to correctly decode the subsequent data section 78 which lasts several tens of bytes to several hundred bytes, thereby extremely deteriorating the whole error rate.
A device for detecting a data sync signal is disclosed, for example, in JP-A-2000-100084. This device is intended to produce a high ability to detect the data sync signal by correcting a discrimination error, if any, of the data sync signal. With this device, as shown in FIG. 28, input data 411 are discriminated by a data discriminator 401, and an output signal 412 thereof is input to a postcoder 402 for the data and a postcoder 403 for the data sync. The data postcoder 402 subjects the output signal 412 of the data discriminator 401 to the postcoding process (bit operation) and produces an output signal 415. This postcoding process generally corresponds to the preceding process for recording in order to assure correspondence between the data coding for recording and the decoding for reproduction.
The data sync postcoder 403, on the other hand, subjects the output signal 412 of the data discriminator 401 to a postcoding process (bit operation) different from that of the data postcoder 402, and produces an output signal 413. This postcoding process corresponds to a data sync signal detection method to assure an optimum detection of a data sync signal.
The output signal 413 of the data sync postcoder 403 is input to a data sync signal detector 404 which detects a data sync signal by comparing the signal with a predetermined sync pattern. Upon detection of a sync signal, a sync signal detection output 414 is produced and gives a timing for decoding a postcoded output signal 415 in a decoder 405 which outputs a decoded output data 416.
Even with this configuration, a further improvement in the detection rate of the data sync signal is desired in view of the fact that the data section is accompanied by an error correction code for correcting a discrimination error and that the requirement of increasing the amount of information recorded per unit area of an information recording medium as far as possible to reduce the cost necessitates the correct data reproduction even with a deteriorated reproduced signal quality.
A related technique is described in a reference entitled “Distance Enhancing Codes for E2PRML: Performance Comparison using Spinstand Data”, by Steven G. McCarthy, Zachary A. Keirn, et al., IEEE. Trans. Magn. Vol. 33, No. 5, September 1997. This reference reports a research in which the performance of various codes for improving the reproduction performance are compared using spindstand data. In this reference, a method of producing the coding gain of 2.2 dB is disclosed in which the (1, 7) code constituting the (d, k) code having a code rate of 2/3 is combined with a Viterbi decoder of EEPRML (extended extended partial response with maximum likelihood detection) type having a reduced number of states to enhance the inter-code minimum square distance from 6 to 10 without considering the code rate loss. In this method, however, the code rate is as low as 2/3. Thus, the bit interval is required to be reduced as compared with other codes of high code rate for recording the same amount of information, and therefore the performance cannot be improved.
JP-A-8-096312, on the other hand, discloses a method in which a pattern having no continuous data inversion is used as a data sync signal.
Further, JP-A-11-251927 discloses a method for discriminating the data sync signal (sync bytes) and the data code string in the configuration of what is called the time varying MTR (maximum transition run) trellis. According to this method, the data sync signal is detected regardless of the time limit, while the data code string is detected according to a time limit. Also in this case, the detection of the data sync signal is dependent on the limit of the data code string, and what can be achieved is not more than the trellis with the limited path of the time varying MTR trellis of the data code string. In other words, since the decoding of a time limited code is presupposed, the data sync signal can be detected in a state equivalent to the highest detection accuracy in the state of the data code, but the data sync signal cannot be detected with higher accuracy than for the data code discrimination.
Furthermore, JP-A-11-339403 discloses a method in which the state of a Viterbi decoder is limited when decoding the signal in the VFO (variable frequency oscillator) field corresponding to the PLO sync section according to the invention described later. In this method, however, although the accuracy can be improved for the bit sync (i.e. the clock reproduction) for the data, the detection performance of the data sync signal cannot be improved in view of the fact that the data sync signal is detected by detecting the data start position in the same state of the Viterbi decoder as when the data portion is detected. The performance can be improved only slightly by the fact that the bit sync accuracy for the data is improved for a higher accuracy of clock reproduction.